| Summary: | 博士 === 國立交通大學 === 電子研究所 === 106 === Nowadays, the smart power technology has been developed and used to fabricate the display driver circuits, power switch, motor control systems, and so on. However, the process complexity and the reliability of high-voltage (HV) devices have become more challenging compared with the low-voltage (LV) devices. Among the various reliability specifications, on-chip electrostatic discharge (ESD) protection has been known as one of the important issues in HV integrated circuits (ICs). ESD is an inevitable event during fabrication, packaging and testing processes of integrated circuits. ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress energies.
In Chapter 2, the modified silicon-controlled rectifier (SCR) fabricated in a 0.25-μm HV Bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective ESD protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high holding voltage of up to ~30 V in the 100-ns Transmission- line-pulsing (TLP) measurement results. However, through the experimental verification by using transient-induced latchup (TLU) test, the holding voltage of such proposed device decreases to ~20V. It is due to the increased bipolar junction transistor (BJT) current gains of the SCR path induced by the Joule heating effect in the long-term measurement. Such phenomenon is an unavoidable issue that should be carefully taken into consideration when applying SCR device for ESD protection in the HV applications.
In Chapter 3, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using LV devices with stacked configuration For HV applications. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-model (HBM) ESD stress. Moreover, stacked LV devices with sharing path technique can be more area-efficient to implement the whole-chip ESD protection in the HV CMOS ICs.
In Chapter 4, the optimization of guard ring structures to improve latchup immunity in an HV double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has been investigated in a silicon test chip. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity.
In Chapter 5, the latchup path which may potentially exist at the interface between HV and LV circuits in a HV BCD technology has been investigated. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic SCR path featuring a very low holding voltage is found in the experiment silicon chip. It may influence the ESD robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at HV and LV interface should be carefully defined to avoid the occurrence of unexpected parasitic path.
Chapter 6 summarizes the main results of this dissertation, where the future works based on the new proposed designs and test structures are discussed as well. The related works in this dissertation have been published in several international journals or conferences.
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