| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 106 === Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing low power designs, which can e ectively reduce the leakage power by turning o inactive circuit power domains. However, power switch allocation needs enough space around macros or SRAM, and the common method of macro place- ment is not applicable. Moreover, people has a habit to place marco manually. With the increasing number of macros in ASIC design, macro placement with distributing minimal space for power switches is a tedious work for designer and costs much time. In this thesis, we propose an e cient and automatic macro re- oorplan framework, which can honor the initial macro oorplan made by designer and generate a ooplan to keep enough space for power switch. In addition, our methedology could judge which macros could be shared power switch ring to save design area. The approach includes a patteren based al- gorithm to overcome non-square-shaped design area and a macro legalization methodolgy with directed acyclic grpah and linear programing. The proposed framework is compli- ant to commercial APR tools and has been integrated into physical design ow in major design-service companies.
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