Study on the Source/Drain Engineering of InGaAs MOSFETs and FinFETs

• Main Authors: Lin, Jia-Wei, 林家緯
• Other Authors: Lee, Chien-Ping
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/zzspx2

碩士 === 國立交通大學 === 電子研究所 === 106 === III–V compound semiconductors have been considered as the new channel materials for the future extremely scaled complementary metal oxide semiconductor (CMOS) devices due to their expected high injection velocity and electron mobility. However, one of the key challenges in realizing high performance III–V nMOSFETs is the reduction of source/drain (S/D) resistance (RSD). Due to nature low dopant solid solubility and high diffusivity of III-V based materials, a high RSD is disappointing the performance of III-V based MOSFET devices. In this study, we propose two methods to deal with source/drain engineering for In0.53Ga0.47 MOSFET devices. First is using a kind of self-aligned metal source/drain technique combined with Silicon implantation in reducing sheet resistance (RSHEET), contact resistance (RC) and resistivity to improve device performance. Second is using microwave annealing (MWA) to active implanted dopants. Due to its low thermal budget, MWA results in fewer dopants diffusion, being beneficial in the S/D formation with the shallow junction and low resistivity. In this study, these two methods are first demonstrated on In0.53Ga0.47As MOSFETs. In addition, utilizing MWA technique, the In0.53Ga0.47As FinFET devices with WFin down to 20 nm and Lch down to 80 nm have been fabricated and characterized. The scaling metrics for In0.53Ga0.47As FinFETs are also systematically studied with LCH from 200 nm to 80 nm and WFin from 60 nm to 20 nm which show an excellent immunity to short channel effects.