Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations

碩士 === 國立交通大學 === 電子研究所 === 106 === This thesis focuses on analog low-dropout linear voltage regulator and digitally controlled linear voltage regulator with FinFET, TFET and Hybrid TFET-FinFET implementations. We use Sentaurus atomistic 3D TCAD mixed-mode to analysis fundamental physical characteri...

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Main Authors: Chang, Chia-Ning, 張珈寧
Other Authors: Chuang, Ching-Te
Format: Others
Language:en_US
Published: 2017
Online Access:http://ndltd.ncl.edu.tw/handle/88x5h8
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spelling ndltd-TW-106NCTU54280182019-05-16T00:08:11Z http://ndltd.ncl.edu.tw/handle/88x5h8 Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations 鰭式場效電晶體與穿隧式場效電晶體於低壓降線性穩壓器應用之探討與分析 Chang, Chia-Ning 張珈寧 碩士 國立交通大學 電子研究所 106 This thesis focuses on analog low-dropout linear voltage regulator and digitally controlled linear voltage regulator with FinFET, TFET and Hybrid TFET-FinFET implementations. We use Sentaurus atomistic 3D TCAD mixed-mode to analysis fundamental physical characteristics of transistors. Also, Verilog-A look-up table calibrated with simulation results from TCAD is applied in HSPICE circuit simulation tool for further analysis. In exploration of analog low-dropout linear voltage regulator (LDO), because the transport mechanism of TFET is different from conventional MOSFET and FinFET, we do investigation of transconductance, output resistance and intrinsic gain of devices at first. It can be observed that, TFET demonstrates better performance at low operating voltage, while FinFET exhibits outperformance in current drive ability which is an advantage in high-performance applications. Furthermore, the performance of FinFET-LDO, TFET-LDO and Hybrid-LDO including frequency response, transient response and power supply rejection ration (PSRR) are evaluated. The results indicate that for ultra-low power application, TFET-LDO and Hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under comparable operating current design. As operating voltage further reduced, the performance of analog LDO degrades severely; therefore, digitally controlled linear voltage regulator becomes the choice. Firstly, we analyze the digital error detector (DED) based on FinFET and TFET at 0.5V operating voltage. The sense period of TFET-DED is 7x times longer than FinFET-DED. Next step, we investigate the performance of pull/push devices under FinFET, Hybrid and Parallel structures based on FinFET-DED. The results demonstrate FinFET applied in digitally controlled voltage regulator stands out at 0.5V operating voltage due to the relatively strong current drive ability. Chuang, Ching-Te 莊景德 2017 學位論文 ; thesis 72 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立交通大學 === 電子研究所 === 106 === This thesis focuses on analog low-dropout linear voltage regulator and digitally controlled linear voltage regulator with FinFET, TFET and Hybrid TFET-FinFET implementations. We use Sentaurus atomistic 3D TCAD mixed-mode to analysis fundamental physical characteristics of transistors. Also, Verilog-A look-up table calibrated with simulation results from TCAD is applied in HSPICE circuit simulation tool for further analysis. In exploration of analog low-dropout linear voltage regulator (LDO), because the transport mechanism of TFET is different from conventional MOSFET and FinFET, we do investigation of transconductance, output resistance and intrinsic gain of devices at first. It can be observed that, TFET demonstrates better performance at low operating voltage, while FinFET exhibits outperformance in current drive ability which is an advantage in high-performance applications. Furthermore, the performance of FinFET-LDO, TFET-LDO and Hybrid-LDO including frequency response, transient response and power supply rejection ration (PSRR) are evaluated. The results indicate that for ultra-low power application, TFET-LDO and Hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under comparable operating current design. As operating voltage further reduced, the performance of analog LDO degrades severely; therefore, digitally controlled linear voltage regulator becomes the choice. Firstly, we analyze the digital error detector (DED) based on FinFET and TFET at 0.5V operating voltage. The sense period of TFET-DED is 7x times longer than FinFET-DED. Next step, we investigate the performance of pull/push devices under FinFET, Hybrid and Parallel structures based on FinFET-DED. The results demonstrate FinFET applied in digitally controlled voltage regulator stands out at 0.5V operating voltage due to the relatively strong current drive ability.
author2 Chuang, Ching-Te
author_facet Chuang, Ching-Te
Chang, Chia-Ning
張珈寧
author Chang, Chia-Ning
張珈寧
spellingShingle Chang, Chia-Ning
張珈寧
Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
author_sort Chang, Chia-Ning
title Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
title_short Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
title_full Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
title_fullStr Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
title_full_unstemmed Exploration and Evaluation of Low-Dropout Linear Voltage Regulator with FinFET, TFET and Hybrid TFET-FinFET Implementations
title_sort exploration and evaluation of low-dropout linear voltage regulator with finfet, tfet and hybrid tfet-finfet implementations
publishDate 2017
url http://ndltd.ncl.edu.tw/handle/88x5h8
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