Timing-driven detailed routing
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === With the rapid development of VLSI technology, the chip size continues to shrink and manufacturing process can reach 7 nm technology node and beyond, so the issue associated with timing becomes very important. When considering timing, it is crucial to reduce...
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| Format: | Others |
| Language: | zh-TW |
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2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/a74nm3 |
| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === With the rapid development of VLSI technology, the chip size continues to shrink and manufacturing process can reach 7 nm technology node and beyond, so the issue associated with timing becomes very important. When considering timing, it is crucial to reduce the interconnection delay of the critical sink and decrease timing delay violations. In this work, we propose a detailed router that can consider the timing issue in the initial routing to find a good routing topology to reduce the interconnection delay of critical sink and optimize the delay for the worst three percent of delay of all nets in the re-routing stage. Experimental results show that our algorithm can effectively reduce the interconnection delay of the critical sink.
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