Process Fabrication and Temperature Characterization of Schottky Barrier Silicon Nanowire Charge-Trapping Memories

• Main Authors: TSAI, JR-JIE, 蔡智傑
• Other Authors: SHIH, CHUN-HSING
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/2m97k3

博士 === 國立暨南國際大學 === 電機工程學系 === 106 === This dissertation studies process fabrication and associated characterization of Schottky barrier silicon nanowire charge-trapping memories. Three fabrication techniques were employed to form gate-all-around nanowire structures, including wet etching, sidewall spacer, and direct-write electron beam lithography. Two metals, nickel and titanium, were utilized to fabricate the Schottky barrier source/drain. The wet etching and sidewall spacer techniques can be utilized to fabricate nanowire structures without the need of advanced lithography. However, electron beam lithography should be utilized to ensure precise control of nanowire diameters for favorable cell characteristics. Temperature of rapid thermal annealing higher than 500 ℃ is required to form the nanowire source/drain with nickel silicide, whereas a higher annealing temperature is needed for titanium-based or phosphorous-incorporated devices. Characterization results show that the on- and off-state cell reading currents depend on operating temperatures, while the cell programming and erasing are relatively insensitive to variations of device temperatures. The fabricated cells preserve excellent thermal retention either at room or higher temperatures.