94 GHz Down-Mixer With Inverter-Based RF Stage And IF Load Technology With Negative Resistance Compensation

• Main Authors: Chen, Ching-Chiang, 陳靖強
• Other Authors: Lin, Yo-Sheng
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/z5gjqz

碩士 === 國立暨南國際大學 === 電機工程學系 === 106 === This thesis mainly use a standard TSMC 90 nm CMOS process to implement 94GHz down conversion mixers. This thesis research three kind of a circuit structure: The first architecture is a 94GHz down conversion mixer. This circuit reform the first architecture by the original inverter circuit and change double-balanced Gilbert circuit resistance into PMOS negative resistance compensation technology for raising conversion gain and compressing power consumption. The second is also a 94GHz down conversion mixer using the Ultra Low Power Diode (ULPD) architecture, which reduces current input compared to the resistance of a typical circuit architecture, resulting in reduced power consumption. The third is a 180GHz down conversion mixer using an Ultra Low Power Diode (ULPD) and a negative resistance compensation architecture. The ULPD architecture reduces current consumption compared to typical circuit architectures, resulting in reduced power consumption, and negative resistance compensation architecture Can improve conversion gain. The last part is conclusion.