| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 106 === Advances in the computer vision have enabled various smart applications in the con- sumer market. Some products, such as wireless sensor networks or smart toys, may require a low-complexity visual object detection unit, in which area and energy efficiency are of con- cerned. This poses a challenge to the designers. In this work, a flexible yet area-efficient object detector based on Viola-Jones algorithm is presented as a base design. To reduce the area while maintaining sufficient throughput, on-chip memories (such as SRAM) are par- titioned into several banks. However, accesses to the same bank may conflict, since the accessing port of each banks are limited. Resolving conflicts is non-trivial due to the fact that the memory access pattern of the detection task depends on the result of machine learn- ing, which is often unpredictable before training. Therefore, we propose an approach which explicitly schedules the access sequence as a post-processing performed after training the object model. As a consequence, memory access conflicts can be avoided. An FPGA imple- mentation is used to verify the idea, and is given at the end of this study. The result shows that by using the proposed methodology, the flip-flop utilization can be drastically reduced. Moreover, the overall area-efficiency is also improved.
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