Analysis and Research of Multi-level Computing Architecture

• Main Authors: Shan-WenChen, 陳善文
• Other Authors: Jer-Min Jou
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/9ex6ga

碩士 === 國立成功大學 === 電機工程學系 === 106 === This thesis focuses on the research of parallel multi-core processor architecture. Firstly, it analyzes the Multi-Level Computing Architecture (MLCA) which is established by SystemVerilog, and deeply understands the execution behavior of the parallel control processor (CP) of the upper task level. After that, the lower processing unit (PU) and the peripheral memory are designed to implement the MLCA parallel multi-core architecture; the upper layer CP of the MLCA is responsible for analyzing and recording the dependencies between tasks during execution, and assigning the ready tasks to the parallel PUs. Execute and pass the execution result back to the CP record. Three different experiments were performed for this system. The experiment was performed with a multi-level computing architecture MLCA multi-core architecture to perform different task programs, including inner product, fast Fourier transform and eight queen experiments. We analyzed three task tests. The execution behavior of the program and verify the correctness of the execution results of the processor unit in the MLCA. Finally, summarize and analyze the three experiments separately, and then discuss them comprehensively because of the experience gained by these three experiments on our MLCA system.