Development of Efficient VLSI Hardware Accelerators and Algorithm for Secure Cloud Computing

• Main Authors: Jheng-HaoYe, 葉正濠
• Other Authors: Ming-Der Shieh
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/5g2k2h

博士 === 國立成功大學 === 電機工程學系 === 106 === With the rapid increase in cloud computing applications, the security issue has become an important research topic nowadays. Fully homomorphic encryption (FHE) allows computations to be carried out directly on encrypted data for ensuring data privacy on untrusted servers. However, FHE demands extremely high computational complexity since large integer multiplication and noise reduction operation are needed for homomorphic evaluation on ciphertexts. In this dissertation, an efficient exclusive-or sum-of-products (ESOP) minimization algorithm based on a novel cost function is presented to simplify the evaluation function on plaintexts, which can relax the need of performing the recryption operation on ciphertexts accordingly. To speedup FHE operations and reduce resource requirements, three low-complexity VLSI architectures of large integer multiplication are presented. First, a novel and efficient operand reduction scheme is proposed to reduce the area requirement of high-radix butterfly units. We also extend the single-port, merged-bank memory structure to the design of the number theoretic transform (NTT) and the inverse NTT (INTT) for further minimizing area costs in both the memory-based and pipelined shared-memory NTT architectures. In addition, a unified memory addressing scheme is developed to support both NTT/INTT and resolving carries computations. Furthermore, an efficient block product reduction scheme for a block-based integer multiplication algorithm is presented. The developed block-based integer multiplier can support various precision of input operands for different FHE applications. Experimental results reveal that significant area reductions can be achieved for all the three architectures of large integer multiplication designed using the proposed schemes compared to related works. To ensure the security of data transmition between cloud servers and users, public-key cryptography (PKC) has gained increasing attention in wireless communication systems and Internet services for providing security features, such as confidentiality, authentication, data integrity, and non-repudiation. In this dissertation, a data dependency relaxation scheme is also proposed to reduce the power consumption of the conventional word-based Montgoemry modular multiplier. The dependency graph is first divided into a set of blocks for handling any precision of operands. Together with the developed architecture mapping scheme, the current words of variables for each processing element in a block interation can be efficiently reused so that the switching activity of pipelined registers and the number of memory access of the kernel in the mapped architecture are greatly reduced. Experimental results show that the proposed scalable architecture achieves significant energy reduction in comparison with related works.