| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系 === 106 === In recent years, the semiconductor industry and the government agencies on national security and defense are starting to pay attention to hardware security issues, including the idea of inserting malicious logic gates into integrated circuit, which we call hardware Trojans.
Since hardware Trojans are stealthy in nature and triggered only under rare conditions, which make them hard to detect. Traditional Trojan activation methods rely on applying random patterns to trigger Trojan circuit; unfortunately, this approach is not efficient in general.
In this paper, we discuss how to construct combinational Trojans efficiently. A set of candidate trigger signals is obtained first, and then dependency among those signals is analyzed so that efficient trigger conditions can be constructed. Since many trigger conditions are not valid when layout constraints are taken into account, we propose a layout-aware approach for Trojan construction and activation vector generation.
According to the experimental results, the number of activation vectors is significantly reduced with the help of layout information. The results of this study should be helpful to the development of Trojan detection methods.
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