Fast Encoding Algorithms and DSP-based Decoder for H.265/HEVC Standard

• Main Authors: Jung-Yang Kao, 高榮揚
• Other Authors: Chou-Chen Wang
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/2r4prp

博士 === 義守大學 === 電子工程學系 === 106 === The new high efficiency video coding (HEVC) standard approved as ITU-T H.265 (H.265/HEVC) facilitates the realization of ultrahigh-definition (UHD) video applications. Although the compression efficiency of the H.265/HEVC coding standard is double that of H.264/AVC, it incurs a very high encoding complexity. In order to reduce the encoding complexity of H.265HEVC, we proposed some fast encoding strategies including coding unit (CU) depth range decision algorithm, neighboring-blocks-based reference frame decision algorithm (NRFDA) and priority-based reference frame selection algorithm (PRFSA). In addition, in order to reach real-time video applications of H.265/HEVC decoder, we also embedded a highly efficient DSP-based OpenHEVC on ADSP-BF548 processor. To speed up the encoding procedure of H.265/HEVC, a fast CU depth range decision is firstly proposed to reduce the searching range. Based on the depth information correlation between tempo-spatial adjacent CTUs and the current CTU, some depths can be adaptively excluded from the depth search process in advance. The best depth of current CTU is determined by an intersection between temporal predicted depth ranges by 9 Gaussian weightings and spatial predicted depth ranges by 4 best weightings from encoded blocks. Secondly, there are same characteristics existing multiple reference frame motion estimation (MRF-ME). To speed up the MRF-ME process, we proposed NRFDA and PRFSA to reduce the computational complexity. NRFDA select the reference frame of the current block from its neighboring blocks due to a high possibility to be all the same optimal reference frame. PRFSA analyses the RD cost correlation between AMVP (JAMVP) and ME (JInter) in MRF-ME process. Therefore, PRFSA defines the priority for each reference frame so that ME can perform on the reference frames along the descending order of priority according to JAMVP. Finally, we integrated three above-proposed methods into finishing a fast H.265/HEVC encoder with insignificant loss of image quality. To realize an embedded fast H.265/HEVC decoder on ADSP-BF548 processor, we proposed a flexible memory assignment architecture (FMAA) to efficiently control memory. In H.265/HEVC decoder, the most consuming processes are motion compensation (MC) and inverse quantization/inverse integer cosine transform (IQ/IT) modules. To reduce the decoding time, the proposed FMAA assigns the functions of MC and IQ/IT from L3 DDR-RAM to L1 and L2 SRAM. The proposed DSP-based H.265/HEVC decoder is based on the open source OpenHEVC. Experimental results show that the proposed method can achieve an average acceleration of H.265/HEVC decoding about 2.5 and 6 times when compared with the directly embedded OpenHEVC and HM16.7 on ADSP-BF548, respectively. It can actually reach real-time decoding when we implement our method on multi-core DSP-based hardware with four cores.