| Summary: | 碩士 === 華梵大學 === 電子工程學系碩士班 === 106 === Under the Life is inseparable from the electronic 3c products, the Phase Locked Loop (PLL), which is a very important circuit, is widely used in wired transmission and wireless transmission. Along with the development of technology and the progress of semiconductor manufacturing, the development of the process has made the area of the whole circuit getting smaller and smaller, and, therefore, it can also add more circuits in the same area, saving area and increasing the speed of wafer operation. In the phase-locked loop, the designers usually aim to lower the power consumption, lower the noise, wider the range, and faster the lock. Improve the basic phase-locked loop to achieve better output.
This thesis uses TSMC 0.18um 1P6M 1.8V COMS circuit to process. Mainly is the improvement of voltage-controlled oscillators. Nowadays, wireless communication becomes much more developed. The traditional voltage-controlled oscillator works poorly in noise over a wide range of frequencies. In the fourth chapter, uses the positive and negative characteristics of the traditional ring oscillator and PMOS and NOMS to improve, and sent to the CIC wafer center for wafer off-line, then measured the returned wafer.
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