A Novel Thin Film Transistor with Gate Sheltered Drain Design

• Main Authors: WANG, JIA-SHENG, 王佳勝
• Other Authors: CHIEN,FENG-TSO
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/7wk76e

碩士 === 逢甲大學 === 電子工程學系 === 106 === Polycrystalline silicon thin film transistors have been attracted for using in various fields, including active matrix liquid crystal displays (AMLCDs) and 3-D integrated circuits because of their high carrier mobility and driving current. The technology is the promised candidate for the ultimate goal of building fully integrated flat panel display system-on-panel (SOP) as a controller and memory. However, a high electric field (EF) near the channel/drain region causes several undesirable effects, such as large leakage current, kink effect and hot carrier effect in TFT. In order to overcome those drawbacks, previous studies used a lot of structures such as offset, Lightly Doped Drain (LDD)、Raised Source/Drain(RSD) and Field-Induced Drain(FID) to reduce the high electric field in the device. Although many of these structures can effectively reduce the electric field, increase the parasitic resistance is lowered a lot of on-current, or require additional mask ion implantation and increased process complexity and cost. Therefore, we propose a structure which requires only a few simple processes, without requiring expensive processing steps to improve the practical value of this device. In this paper, we propose a structure entitled “A Novel Thin Film Transistor With Gate Sheltered Drain Design”. Its feature owing to add a additional drain electrode underneath the gate layer, and the sheltered drain is connected to the drain electric potential can distribute the electric field near the channel/drain region because of the potential difference is close to zero. According to our simulation results, the high electric field (EF) and impact ionization (IMP) are substantial improved near the channel/drain region and effectively reduce the leakage current which will make the device have a good ON/OFF current ratio. The new structure also without requiring expensive processing steps and it will be beneficial to circuit efficiency when the devices are applying to large area microelectronics by using our new concept devices.