The Design of 0.2-1.8GHz Duty Cycle Correction Circuit.

• Main Authors: WU, GUAN-WEI, 吳冠葳
• Other Authors: Hsu, Heng-Shou
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/95ce9s

碩士 === 逢甲大學 === 電子工程學系 === 106 === In this thesis, we propose an analog high speed circuit which is fast locking and low error. It is necessary to have precise signal transmission in the modern high speed signal transmission circuit and any signal circuit which need correction. In order to avoid the instability of the circuit system caused by the distortion of the clock signal, PLL(Phase Lock Loops) can be used in the circuit for controlling phase and frequency. PLL(Phase Lock Loops) is generally widely used in the field of electronic communication, for example, computer memory, radio frequency technology, microprocessor, etc. The proposed circuit operation frequency is at 0.2GHz to 1.8GHz, the errors are less than ±1%. The correction circuit is implemented in a 1.8V, and 180nm CMOS technology.