High-Performance VLSI Design for Convolution Layer of Deep Learning Neural Networks
碩士 === 逢甲大學 === 電子工程學系 === 106 === Convolutional Neural Networks (CNN) are widely used in modern AI system. This thesis proposed three hardware architectures for the CNN. We named them Design1~Design3. The 1-D Processing Element (PE) is structured by using Weight Stationary (WS) in Design1. Because...
Main Authors: | ZENG, JIAN-LIN, 曾建霖 |
---|---|
Other Authors: | CHEN, KUAN-HUNG |
Format: | Others |
Language: | zh-TW |
Published: |
2018
|
Online Access: | http://ndltd.ncl.edu.tw/handle/dzn4pq |
Similar Items
-
VLSI Design and Implementation to Accelerate Deep Learning Convolution Neural Network
by: Cheng-Hsiang Yang, et al.
Published: (2019) -
Analysis and Comparison of Convolution Layer in Deep Convolution Neural Network
by: Yi-Chun Hu, et al.
Published: (2018) -
VLSI Architecture Design and FPGA Implementation for Depth Separable Convolution Neural Network
by: Yu-Hao Hwang, et al.
Published: (2019) -
The Efficient VLSI Design and Implementation of Neural Networks Based on Depthwise Separable Convolution
by: Hung-Ju Lin, et al.
Published: (2018) -
Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers
by: Jinil Chung, et al.
Published: (2020-01-01)