Design and Implementation of a Side-Channel Attack Resistance Verification System

• Main Authors: PENG, SHAO-YU, 彭紹宇
• Other Authors: HONG, WEI-CHIH
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/kcb7ev

碩士 === 逢甲大學 === 資訊工程學系 === 106 === The rapid development of wireless and mobile communications and Internet of Things (IoT) devices have undoubtedly caused significant changes to our life. Entering the IoT era, it is crucial to verify the IoT devices’ ability to thwart potential attacks from stealing confidential data. Side-channel attacks (SCAs) are capable of bypassing the theoretical protection of cryptographic schemes and revealing secret information in hardware devices. In recent years, there have been significant breakthroughs in SCAs. They have become a serious threat to the security of the cryptographic modules. In this thesis, we design and implement a framework for efficient SCA resistance verification. By integrating trace measurement equipment and GPU-accelerated analyzing engines, we have successfully built an automatic system which greatly simplifies the test procedure and enables on-the-fly SCA tests. Experiment results on common IoT development boards show both promising strength and flexibility of our framework to meet different testing requirements smoothly.