Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction

碩士 === 中原大學 === 電子工程研究所 === 106 === This thesis proposes two-clock circuit model and a method of pattern compaction. We first eliminate all flip-flops, copy the remaining circuit, and connect pins between two circuits to complete building two-clock circuit model for generating launch-off-shift (LOS...

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Main Authors:	Hsun-Sheng Chen, 陳勳聖
Other Authors:	Hsin-Tsung Liang
Format:	Others
Language:	zh-TW
Published:	2018
Online Access:	http://ndltd.ncl.edu.tw/handle/tq494t

id	ndltd-TW-106CYCU5428048
record_format	oai_dc
spelling	ndltd-TW-106CYCU54280482019-11-28T05:22:00Z http://ndltd.ncl.edu.tw/handle/tq494t Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction 使用兩時脈電路模型與圖樣壓縮建立位移末投值低功率圖樣 Hsun-Sheng Chen 陳勳聖碩士中原大學電子工程研究所 106 This thesis proposes two-clock circuit model and a method of pattern compaction. We first eliminate all flip-flops, copy the remaining circuit, and connect pins between two circuits to complete building two-clock circuit model for generating launch-off-shift (LOS) patterns for single-chain and double-chain scan designs. We use two-clock circuit model to generate LOS low power patterns by setting stuck at faults and fixed value for a commercial software. Then we use our tool to compact the final low power patterns. Experiments show that we can reduce power for 58.99 percent and number of patterns for 93.77 percent on average for single-chain designs. Hsin-Tsung Liang 梁新聰 2018 學位論文 ; thesis 66 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中原大學 === 電子工程研究所 === 106 === This thesis proposes two-clock circuit model and a method of pattern compaction. We first eliminate all flip-flops, copy the remaining circuit, and connect pins between two circuits to complete building two-clock circuit model for generating launch-off-shift (LOS) patterns for single-chain and double-chain scan designs. We use two-clock circuit model to generate LOS low power patterns by setting stuck at faults and fixed value for a commercial software. Then we use our tool to compact the final low power patterns. Experiments show that we can reduce power for 58.99 percent and number of patterns for 93.77 percent on average for single-chain designs.
author2	Hsin-Tsung Liang
author_facet	Hsin-Tsung Liang Hsun-Sheng Chen 陳勳聖
author	Hsun-Sheng Chen 陳勳聖
spellingShingle	Hsun-Sheng Chen 陳勳聖 Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
author_sort	Hsun-Sheng Chen
title	Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
title_short	Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
title_full	Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
title_fullStr	Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
title_full_unstemmed	Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
title_sort	generate launch-off-shift low power patterns by using two-clock circuit model and pattern compaction
publishDate	2018
url	http://ndltd.ncl.edu.tw/handle/tq494t
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Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction

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