Generate Launch-off-Shift Low Power Patterns by Using Two-Clock Circuit Model and Pattern Compaction
碩士 === 中原大學 === 電子工程研究所 === 106 === This thesis proposes two-clock circuit model and a method of pattern compaction. We first eliminate all flip-flops, copy the remaining circuit, and connect pins between two circuits to complete building two-clock circuit model for generating launch-off-shift (LOS...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/tq494t |
| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 106 === This thesis proposes two-clock circuit model and a method of pattern compaction.
We first eliminate all flip-flops, copy the remaining circuit, and connect pins between two circuits to complete building two-clock circuit model for generating launch-off-shift (LOS) patterns for single-chain and double-chain scan designs.
We use two-clock circuit model to generate LOS low power patterns by setting stuck at faults and fixed value for a commercial software. Then we use our tool to compact the final low power patterns.
Experiments show that we can reduce power for 58.99 percent and number of patterns for 93.77 percent on average for single-chain designs.
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