| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 106 === A system-on-Chip (SoC) design consists of many embedded cores. In order to test these embedded cores, modular wrapper design needs to connect scan elements to form test wrapper chains. Since the longest test wrapper chain affects the test time, how to balance these wrapper chains is an important topic. As the feature size continues to shrink, the wire length has become a serious concern. Three-dimensional integrated circuits (3D ICs) provides a promising solution, but it also brings a challenge in modular wrapper design. Since scan elements in a 3D IC spans multiple layers, we not only need to balance these wrapper chains but also need to reduce the number of through-silicon-vias (TSV) usages. However, previous work only uses a post-processing approach to reduce the TSV count. As a result, the previous work often leads to a large TSV count. Based on that observation, in this paper, we propose a two-stage algorithm for test wrapper chain optimization. Different from the previous work, our objective is to minimize the test time under the given TSV number constraint.
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