| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 106 === In order to save the excessive margin, different types of timing sensors have been developed and adaptive voltage scaling is adopted [2]-[10], like Razor I. In 90nm technology, Razor I area overhead is about 27% by simulation due to the short path problem. Although Razor I can be used to save energy by reducing voltage, it cannot be eliminated additional energy. Through the new timing error prediction with local boost scheme(TEP/LB), in addition to ensuring that the circuit can fix the predicted error, it also eliminates the problem of short path. The TEP/LB technique area overhead is only about 12% by simulation. Meanwhile, we speculate the low probability of the circuit occurring in the worst case, so we design in the typical case instead of the worst case for area optimization. This new technology is called variation-resilient typical case design. In order to achieve a true variation-resilient system, the additional circuit should cover all PVT variations to ensure function work. The proposed technology is simulated by a 16-bit multiplier using 90nm technology. In the test chip, the typical-case design multiplier save 30% more area than the worst-case design. In the case of no warning signal and no error, it can save 30% power consumption; if happening warning signals, it can maintain the similar as the power consumption of conventional circuit design.
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