Characterization of Delay Variations on Modern FPGA
碩士 === 國立中正大學 === 資訊工程研究所 === 107 === FPGA (field-programmable gate array) has been widely used in various systems, beyond its original application in ASIC prototyping, and the high volume has pushed it as the new technology driver. Advanced technologies bring the advantages on performance and power...
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| Format: | Others |
| Language: | zh-TW |
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2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/dhrz87 |
| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 107 === FPGA (field-programmable gate array) has been widely used in various systems, beyond its original application in ASIC prototyping, and the high volume has pushed it as the new technology driver. Advanced technologies bring the advantages on performance and power dissipation but also incur significant design variations due to shrink device sizes. This thesis propose a LUT (Look-Up-Table) based ring oscillator design, this method only need programming 2 times on FPGA chip to get every CLB (configurable logic block)’s delay status with NI’s automatic measuring device, and use that result to draw a delay map. Delay map can present the variation in chip, or present the aging effort on chip with multiple delay map.
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