Loop Transformation and Instruction Scheduling Techniques for Timing Speculative Architecture

• Main Authors: TSENG, YU-MING, 曾淯銘
• Other Authors: CHEN, PENG-SHENG
• Format: Others
• Language: en_US
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/as8mgc

碩士 === 國立中正大學 === 資訊工程研究所 === 106 === Traditional processor design incorporates voltage and frequency guardbands to ensure correct execution of operations under worst-case conditions. As transistor density increases and manufacturing processes improve, increasingly costly guardbands are required to deal with the impacts of environmental variability. The use of timing speculation can relax the tight constraint for worst-case design by allowing occasional errors, which are detected and corrected later by an error resilience mechanism. However, a program's performance may suffer owing to timing errors. The thesis consists of three works. First, we analyze program behaviors and observe what influence the number of timing errors through a simulator. Second, we propose a loop transformation technique for Timing Speculative Architectures to reduce up to 37% the number of timing errors. Third, we propose an instruction scheduling technique to rearrange the instructions in the programs that make better cooperation between Timing Speculative Architecture and Adaptive Voltage Scaling technique and reduce up to 45% the number of timing errors. These proposed techniques are implemented in the LLVM compiler infrastructure to generate the optimized programs automatically.