Warpage Simulation and Optimization Analysis of Fan-out Wafer Level Package Process

• Main Authors: LI,YU-JUN, 黎昱均
• Other Authors: Lwo, Ben-Je
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/a5bts3

碩士 === 國防大學理工學院 === 航空太空工程碩士班 === 107 === Fan-out wafer level package (FOWLP) is one of most popular packaging technology in recent years. This is because FOWLP is considered as the key to break through the bottleneck of Moore’s Law, and it provides opportunities for the foundries to participate packaging business. However, FOWLP process is facing the challenges on packaging warpage during manufacturing process due to CTE mismatch between the structure materials. To this end, FOWLP warpage in each process stages were simulated, and a new silicon ring design was proposed to reduce process warpage in this study. To reduce warpages in FOWLP process, Taguchi Methods with different variables were uses to study the optimal factorial combinations on material properties and ring designs. With the results of this study and the new silicon ring designs, warpages on FOWLP process have been effectively reduced and useful information were provided to the packaging industry.