Flexible code length LDPC codec design for high-density solid-state drive systems

• Main Authors: Chen-Pei Song, 宋辰霈
• Other Authors: Cheng-Hung Lin
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/62572232417475897706

碩士 === 元智大學 === 電機工程學系 === 105 === Nowadays, NAND Flash memory is a growing fast product in consumer electronic market. NAND Flash memory has been widely adopted in many electrical devices such as camera, cell phones, and solid state drive due to its high speed, low power and low cost. As technology process and data storage technique continue to improve, the data capacity increases significantly but the data reliability of NAND Flash memory becomes worse. The problem makes BCH code which is applied in traditional NAND Flash memory can not afford such high error rate. Hence, LDPC codes which have better error correcting performance compare with BCH code are start to applied in NAND Flash memory. The thesis adopts LDPC codec to implement error correcting codec design for NAND Flash memory application. Furthermore, NAND Flash memory has many page sizes for different applications and the different page sizes makes codec need to modify parity check matrix for multiple code length. In LDPC code, the codec needs to be redesign for different parity check matrix. Considering the application flexibility of LDPC codec design, the proposed LDPC codec can be applied in different page size form 1KB to 4KB by modifying the expending factor of H matrix. Considering area cost and processing speed, we adopted NPMSA algorithm which improves huge area cost and decoding speed with less error correcting performance loss for our LDPC codec design. To further reduce the power consumption, we proposed a partially stopped scheme to discard unnecessary calculation in CNU by detecting the high reliability prior messages. Finally, we implemented a flexible code length LDPC codec design for high-density solid-state drive systems in TSMC 40nm CMOS process with working frequency 384.6 MHz, core size 5.84mm2, minimum decoding throughput 417.6 MB/s, minimum encoding throughput 766.7 MB/s, encoding power consumption 106.4 mW, and decoding power consumption 376.8 mW. The proposed partially-stopped scheme reduces 0.1% average decoding power consumption under 8 iterations with 1.2% area overhead of decoder and the error correction performance degrades about 0.05dB.