| Summary: | 碩士 === 元智大學 === 電機工程學系 === 105 === With the rapid growth of multimedia services, ultrahigh-definition television (UHDTV) are being widely investigated and developed to display very-large-screen video in the television systems. Compared with HDTV systems, UHDTV systems are developed to offer higher transparency to the real world and more accurate visual information. Currently, there are two competing alliances for UHD applications: Wireless HD (WiHD) alliance and Wireless Gigabit (WiGig) alliance. The both alliances target the 60-GHz short-range wireless market that provides products to connect the devices capable of streaming UHD video over a short range. To enable wireless UHD video transmission, the IEEE 802.11ad standard is supported by the WiGig. However, the WiHD supports the IEEE 802.15.3c standard. In order to have a reliable transmission over noisy channels, low-density parity-check (LDPC) codes have been adopted as forward error correcting (FEC) schemes for the IEEE 802.11ad standard and IEEE 802.15.3c standard. The both standards adopted distinct LDPC coding schemes with different parity check matrixes and different code rates. However, the different encoding and decoding approaches for the LDPC codes usually lead to different hardware architectures that increase the design time and hardware costs of chip implementations.
Hence, we will propose a flexible LDPC decoder, it can be support to IEEE 802.11ad and IEEE 802.15.3c standard. According to 8 type parity check matrix, we adopt 8/16/32 reconfigurable of CNU architecture at critical path to switching different code rate, and collocate Normalized Probabilistic Min-Sum Algorithm(NPMSA) of Minimum Value Finder (MVF) to reduce the architecture complexity. Through the CNU we will store extrinsic value to Extrinsic Memory and this memory can against the store value to stored. In Variable Node Unit(VNU) also can calculated according to different size of extrinsic value. Furthermore, by adopting Layer Stopping (LS) criterion and Layer Stopping Number Termination(LSNT) can early terminate the iteration and then reduce power consumption.
Finally, we propose a LDPC decoder which is based on IEEE 802.11ad process and it will support to eight code rate of dual-standard. The proposed LDPC decoder is implemented in TSMC 40nm CMOS process. The core size is 1.59 mm × 1.59 mm and the maximum operation frequency is 292 MHz. The decoder throughput can be achieved up to 9.3 Gbps.
|
|---|
