| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 105 === The market demand for automatic test equipment (ATE) requires a higher data transfer rate and precision timing to control the device under test (DUT) and test equipment for the test data comparison. The most basic function of ATE is able to complete the digital data transmission correctly. Common logic/functional tests are related to time delay adjustments and must be able to produce corresponding clock signals, including programmable delay, timeset memory and associated circuit to produce the desired timing. This thesis is dedicated to the design of the timing generator that can be applied in ATE.
This thesis first introduces the basic architecture of ATE and the required data formats. Then, the structure of the timing generator is mainly divided into four parts: the timeset memory, the coarse timing generator, the counter and the fine timing generator. The coarse timing generator utilizes delay-locked loop (DLL) to realize the instantaneous switching function which set by the time data from the memory to select output timing. The fine timing generator is designed with an open-loop style which takes the advantage of the look-up table to achieve a very precise resolution.
The proposed timing generator is designed and implemented in TSMC CMOS 0.18μm 1P6M process. The input operating frequency range of DLL is 0.9G ~ 1.2GHz. And the output frequency range of the timing generator is 1.76M ~ 600MHz. After normalization, the fine resolution can achieve 2ps.
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