| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系 === 105 === A three-level converter with novel current doubler rectifier and wide range zero voltage switching (ZVS) is studied and implemented. The main advantages of proposed converter are applicable to high input voltage and high output current, moreover, allowing the switches of lagging-leg to easily achieve ZVS enen if the converter is under light load to full load condition, then the switching loss is reduced and the efficiency of the converter is improved. In high input voltage applications, three-level converter is adopted at primary side and utilizes two input capacitors to connect in series to split input voltage. The flying capacitors and clamped diodes are adopted in order to reduce voltage stress of power switches to half of the input voltage. One half-bridge and one three-level converter shared the lagging-leg switches are used to extend ZVS range of the lagging-leg switches. In high output current applications, the current doubler rectifiers are adopted at secondary side. Two inductors and four diodes are used to reduce output ripple current. Two current doubler rectifiers are connected in series and shared two inductors in order to lessen magnetic elements.
Finally, the detailed circuit analysis and design consideration for the proposed converter are presented in this thesis. The proposed converter is verified by simulation results and implementation with input DC voltage 750V~800V, output voltage 48V, output current 30A and total output power 1440W. The experimental results show that the efficiency of the converter is more than 90% at full load condition.
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