High Gain-Bandwidth and High Slew Rate Multi-Stage Amplifier Design

• Main Authors: TSAI, SHENG-DA, 蔡昇達
• Other Authors: KUO, PO-YU
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/g456p7

碩士 === 國立雲林科技大學 === 電子工程系 === 105 === This study presented a High Gain-Bandwidth and High Slew Rate Multi-Stage Amplifier and it significantly improves the DC gain, gain bandwidth and slew rate of traditional recycling folded cascode amplifier. By applying the high-gain and high-speed circuit, high-speed current loop, and shunt current sources, the dc gain, gain bandwidth, and slew rate of the proposed amplifier can be enhanced. The proposed circuit has been implemented and verified using TSMC 0.18um 1P6M CMOS process with 1.8V power supply and 5pF capacitor load. From the simulation results, the proposed amplifier can achieve 105.5dB DC gain, 66.996V⁄μs slew rate, 206.36MHz gain-bandwidth and 53° phase margin. The simulation results also show that the proposed circuit achieve better DC gain, gain-bandwidth, and slew rate comping with the folded cascade amplifier and related works.