Design and Implementation of a Digital-Controlled and Interleaved Active-Clamp Flyback Converter with Synchronous Rectification
碩士 === 國立臺北科技大學 === 電機工程系所 === 105 === The purpose of this thesis is to design and implement a digital-controlled and interleaved active-clamp flyback converter with synchronous rectification. Based on the design of active-clamp architecture, the two phases work with interleaved control and use a un...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/at7zrk |
| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 105 === The purpose of this thesis is to design and implement a digital-controlled and interleaved active-clamp flyback converter with synchronous rectification. Based on the design of active-clamp architecture, the two phases work with interleaved control and use a unique clamp capacitor which recovers the energy from leakage inductance to improve shortcomings such as high switch stress and snubber power loss in the traditional flyback converter. All switches have zero voltage switching (ZVS) characteristics in the implemented active-clamp flyback converter to reduce the switching loss and switching noise. The used interleaved control can reduce conduction loss on the transformer secondary side and output voltage ripple. The designed synchronous rectification is applied to reduce the conduction losses further.
The implemented flyback converter specifies the maximum power 500W, the input voltage 380V, the output voltage 24V and the operation frequency 150kHz. The used controller is DSP TMS320F28035 produced by Texas Instruments. It is verified that the efficiency reaches more than 95% at full load and the waveform and overall circuit loss analysis can be proved with the simulation software PSIM.
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