3D IC Floorplanning Based on Parallel Simulated Annealing and Delay Aware
碩士 === 國立臺北科技大學 === 電機工程研究所 === 105 === So far, using Through-Silicon Via (TSV) to package the 3D IC is the trend. Most floorplanning researches focus on the number of TSVs, area and wire length, but the calculating of lower cost takes much time. Moreover, the more TSVs and longer wire-length make m...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/3ny4tr |