Power Loss Reduction Study on UMOS Device

• Main Authors: WU,CHING-YUAN, 吳景淵
• Other Authors: YANG, SHAO-MING
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/vmg6f5

碩士 === 亞洲大學 === 資訊工程學系 === 105 === With advances of semiconductor technology, integrated circuit, power device, switching device and motor driver are growth fast. The research focus on Power loss. The U-Sharped Trench MOSFET device is most of important. The reason is UMOS have Lowest On-Resistance and Operating range can be up to 200v. On-Resistance means when the power device turn-on it will cause power loss. And the UMOS are vertical U-Sharped trench design it is better than horizontal device. Due to vertical U-Sharped trench it can significantly reduce the chip size and increase the intensity. Focus on this thesis used the Technology Computer Aided Design (TCAD) tool to develop the UMOS structure and reference by Technology company like Fairchild、Texas and TSMC specification to build the measurement circuit doing the Gate charge simulation、Switching loss measurement and Capacitance to analyze and improvement UMOS. Therefore, based on UMOS figure of merit = O