A Modified BAST for Test Data Reduction Using Correlation of ATPG Pattern
碩士 === 南臺科技大學 === 電機工程系 === 105 === In order to reduce the test data for BAST (BIST-Aided Scan Test), an LFSR reseeding circuit with additional MUXs (Multiplexer) and NOT gates are proposed. The procedure to generate the control signals for optimal reseeding of the circuit are proposed by making co...
Main Authors: | CAI, ZHENG-HONG, 蔡政宏 |
---|---|
Other Authors: | 蔡亮宙 |
Format: | Others |
Language: | zh-TW |
Published: |
2017
|
Online Access: | http://ndltd.ncl.edu.tw/handle/5u939p |
Similar Items
-
Transition Fault ATPG Based on Stuck-At Fault Test Patterns
by: Yan-Nan Lin, et al.
Published: (2006) -
ATPG and Test Compression for Probabilistic Circuits
by: Kai-Chieh Yang, et al.
Published: (2018) -
Reducing Test Pattern Count by A Parallel N-pattern Compaction ATPG
by: Bo-Yi Li, et al.
Published: (2018) -
Ring Counter Based ATPG for Low Transition Test Pattern Generation
by: V. M. Thoulath Begam, et al.
Published: (2015-01-01) -
DFT and ATPG of Two-pattern Tests for Dual-rail Asynchronous Circuits
by: Ying-Hsu Wang, et al.
Published: (2015)