| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === Phase Lock Loop (PLL), the most important role in radio frequency (RF) communication system, generates fixed frequency for transceiver, so that the transceiver can transmit/receive the correct signal and reduce the impact of noise. PLL consists of Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In order to pursue low-power, low phase noise and wide locking range: the most important characteristics of performance of VCO and Divider, this thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).
First, we discuss the locking range property of a CMOS wide locking range divide-by-3 injection-locked frequency divider (ILFD), this chip uses standard 0.18 μm BiCMOS process and die area is 0.859 × 0.817 mm2. The ILFD circuit bases on capacitive cross-coupled oscillator and uses dual-resonance RLC resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 5.26 mW and the locking range is from 6.2 to 12.6 GHz (68.09%) at injection power Pinj = 0 dBm. The dual-resonance ILFD has wide locking range in normal operation with reasonable power consumption. However, the dual-resonance ILFD has three non-overlapped locking ranges for the ILFD biased at higher gate bias for the switching FETs and subject to high injection power. This indicates that the originally designed ILFD using multi-resonance resonator have three non-overlapped locking ranges of a triple-resonance ILFD.
Secondly, we present the RF locking range of divide-by-3 injection-locked frequency dividers (ILFDs) subjected to high injection power larger than 0 dBm. The divide-by-3 ILFD bases on a push-push cross-coupled n-core MOS LC-tank oscillator and uses linear mixer and was implemented in 0.18 μm CMOS process. The locking range can saturate at high injection power and then starts decreasing as injection power further increases. Finally the ILFD stops tracking the injection source.
Thirdly, we propose the RF locking range of divide-by-3 injection-locked frequency dividers (ILFDs) subjected to high injection power larger than 0 dBm. The divide-by-3 ILFD uses nonlinear mixer and was implemented in 0.18 μm CMOS process. Simulation shows the locking range saturates at high injection power and then starts decreasing as injection power further increases. Finally the ILFD stops tracking the injection source. Measurement shows no saturation of locking range, and this is limited by the measurement set-up.
Finally, we study the high-power injection effect of frequency divider from three different architecture divide-by-3 dividers. This measurement result was verified by simulation. The research is very practical for circuit designer, they can avoid saturation phenomenon by higher power injection at design process. This is the largest contribution of my thesis.
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