Design and Implementation of a 12-bit 100-MS/s SAR ADC
碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === This thesis presents a 12bit 100MS/s successive approximation register analog to digital converter (SAR ADC). Sub-ranged SAR architecture is used to achieve 100MS/s sampling rate. This ADC design is based on SAR architecture but with sub-ranged operation. A low...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74411232626403249189 |