| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 105 === In this thesis, we make use of Artificial Neural Network (ANN) approach to analyze the relation between design parameters and eye diagram performance of memory bus. Then we used the trained ANN function to find the optimal design for two kinds of memory structure. One is the one-to-eight CMD/ADDR/CNTR buses in flyby structure in DDR2 (Double-Data-Rate Two Synchronous Dynamic Random Access Memory).With ANN, we tried to design the structure in higher degree of freedom, but it didn’t help us to get much higher performance results. Therefore, we utilize the equivalent circuit to investigate the key point that effects the performance. Nevertheless, well-trained ANN can quickly suggest the design guideline for different demand in same structure. We find that when the total length of the flyby structure is not long (<0.3λ),it is easy to approach optimal design by letting the characteristic impedance higher.
For another one we analyze the Low Power DDR4 (LPDDR4) transmission line design in the lower redistribution layer in InFO-WLP (Integrated Fan-Out Wafer-Level-Packaging) technology used for mobile devices with ANN. In different kinds of unit cell, we analyze the effect of design parameters on the performance and finally use the equivalent circuit to certify our result.
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