Research of 40nm LDMOS Multi-Way Transformer Combined and 65nm CMOS Pre-Distortion Linearized Power Amplifier

• Main Authors: Feng-Yu Hsu, 許峰毓
• Other Authors: 黃天偉
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/21597461839948372276

碩士 === 國立臺灣大學 === 電信工程學研究所 === 105 === With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuits implemented in CMOS technology become the key point in the industry with low cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is the design and analysis of CMOS power amplifier [31]. The chapter 2 describes a 4G-LTE power amplifier, which is implemented in 40 nm laterally diffused metal oxide semiconductor (LDMOS) CMOS process. To increase the output power, the circuit uses transformer-based matching network for input and output. The proposed PA is designed in a differential common source structure. The neutralization technique is also implemented in this PA design to reduce the intrinsic capacitance from drain to gate. The chip size of the PA is 0.62mm2 and the output saturation power achieves 23.1dBm. The chapter 3 describes a fully-integrated Wi-Fi power amplifier, which is implemented in 40 nm LDMOS process. By current-current combining transformer technique, the multiple transformers can be realized in a compact area with similar port impedance. In addition, the PA uses 3-D radial architecture to reduce the area of multi-way combining. The chapter 4 describes a 29 GHz power amplifier in 65 nm CMOS process. In this work, the PA is designed with pre-distortion linearizer and the circuit uses transformer-based matching networks for input and output network. This power amplifier improves the OP1dB and linearity. Index term-Power amplifier, Transformer combining, High operating voltage, Pre-distortion power amplifier