TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures

• Main Authors: Chien-Hong Teng, 鄧建鴻
• Other Authors: 林浩雄
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/g73uyt

碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.