A Low Voltage Subharmonically Injection-Locked PLL in 90-nm CMOS Technology

• Main Authors: Bo-Wei Huang, 黃柏崴
• Other Authors: 陳中平
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/26825144118781154542

碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === Based on the advance of the Internet of Things (IOT), the applications of biomedical IC become popular. Due to the limits of electric power consumption by the battery, the issue related to low power design for circuits is more important. The 0.5V voltage can be provided by solar cell in portable devices. According to the reports proposed by International Technology Roadmap for Semiconductor (ITRS), supply voltage of general low-power circuits will be scaled down to 0.5V for the next generation applications. The phase-locked loop (PLL) is an essential circuit for providing a reference frequency signal in a system on chip (SOC). However, the current of circuit is lower under an intrinsic low-voltage environment, and operating frequency of PLL circuit is restricted. In addition, the phase noise of oscillator in PLL circuit is more significant in low voltage design. In this thesis, we proposed two methods to improve the problems of low voltage PLL. The modified bootstrapped technique is adopted to increase the operating frequency of the oscillator under supply voltage of 0.5V. The differential bootstrapped technique increases not only the swing of oscillator, but also the driving current of MOSFET. The gate-switch technique is then introduced to the charge pump in order to increase operation range. The injection-locked technique is adopted to suppress the noise and jitter of VCO. The traditional manual injection-locked is design in this work, besides, the automatic injection-locked is also realized. This work for low-power design is implemented in standard 90nm CMOS technologies. The core area is 0.108mm , and it is operated between 330MHz to 700MHz at 0.5V supply voltage with the locking range. The fabricated circuit is consumed a dc power of 333.5μW which is lower than general requirement. Under the manual injection-locked, the phase noise at 1MHz offset and RMS jitter are -106.56dBc/Hz and 5.5ps, respectively.