| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === In this thesis, an RF front-end which is a sliding IF receiver including a low-noise amplifier, a first stage down-conversion mixer and an I/Q mixer as the second stage are proposed in a 1.1-V supply. The first stage of proposed RF front-end presents a variable gain control low noise amplifier to keep different input magnitude from saturation of circuit. This work is fabricated in TSMC 40-nm CMOS technology. The total power consumption is 15 mW, the highest gain is 10 dB and noise figure is 5.8 dB at 36 GHz. The variable gain control can adjust the gain more than 10 dB.
The following stage is a down-conversion mixer which converts frequency from 36 GHz to 7 GHz. The work introduces a current-bleeding technique to improve the noise figure. This work is fabricated in TSMC 40-nm CMOS technology. The total power consumption is 4.5 mW. With some EM model uncertain, the conversion gain is -20.8 dB
and input P1dB is 6 dBm.
The latest stage is an I/Q down-conversion mixer which converts frequency from 7 GHz to below 1 GHz. Besides, to generate four phase, a CML divider is also implemented. This work is fabricated in TSMC 40 nm CMOS technology. The total power consumption of I/Q mixer including the buffer for measurement is 10 mW. The conversion gain is 17 dB, NF is 8.88 dB and the input P1dB is -14 dBm.
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