Design of 20Gbps Adaptive Linear Equalizer and Decision Feedback Equalizer

• Main Authors: Kuan-Yu Chen, 陳冠宇
• Other Authors: Shen-Iuan Liu
• Format: Others
• Language: en_US
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/rc2864

碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === Nowadays, the SerDes (Serializer-to-Deserializer) topology is increasingly popular in the wireline communication systems for the reduced I/O pads and also the low fabrication cost. However, the aggregate bandwidth of the data traffic is strictly limited by the channel characteristics. The limited bandwidth of the channel will induce large inter-symbol interference (ISI), and also deteriorate the bit-error-rate (BER) performance. Thus, the equalization is more and more important in the wireline systems. Moreover, the channel attenuation greatly varies with materials and lengths, and hence the adaptation techniques for the equalizer are required in most applications. In this thesis, the most common equalizers in the receiver are designed, analyzed, and verified. The first part shows a 20Gbps linear equalizer with the proposed adaptation method. Fabricated in 40nm CMOS technology, this adaptive linear equalizer can well compensate the channel loss under 18.3dB attenuation. Only 2.68us is required for the adaptation procedure and 4.9mW is consumed by the adaptation logics. The second part presents a 20Gbps infinite impulse response decision feedback equalizer (IIR-DFE). To enhance the power efficiency of the IIR-DFE, the charge-steering logic (CSL) is utilized in this work. Besides, the quarter-rate topology and some circuit merging techniques are adopted. Fabricated in 40nm CMOS technology, the power efficiency of 0.31mW/Gbps can be obtained.