A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability

• Main Authors: Chih-Lung Hsiao, 蕭智隆
• Other Authors: 黃俊郎
• Format: Others
• Language: zh-TW
• Published: 2016
• Online Access: http://ndltd.ncl.edu.tw/handle/gt5xda

碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === The formatter plays an important role in automatic test equipment. It is responsible for formatting the test signal with test vectors, signal formats, edge timings and other input data. ASIC designed formatters are more common in the market comparing to ones with FPGA designed, since ASIC formatters achieve higher performance generally. For this reason, ASIC design is the mainstream for formatter. However, FPGA format-ters still have potential, because FPGA design has the advantages of lower development cost, higher flexibility, and no need to tape-out. In this work, the proposed formatter is implemented on Xilinx Spartan-6 FPGA, and it is supported with multiple interval symbol-stretching and symbol inversion func-tions. On-the-fly symbol-stretching is achieve with hardware, and it empowers the for-matter to generate test signals with 100, 50, 33.3, 25 Msps symbol rate without changing the frequency of system clock. The measurement results show that the proposed for-matter achieves 200 ps edge placement resolution and the accuracy is 91 ps.