| Summary: | 碩士 === 國立臺北大學 === 多媒體與網路科技產業碩士專班 === 105 === The simulation and confirmation of the signal integrity of the industrial computer internal bus is a necessary work to ensure the quality of the product. Generally, the simulation tools used for signal integrity are very complicated and expensive as the SIWAVE of ANSOFT. It does not carry out the signal simulation until finish PCB layout. It takes much of time to complete the analysis since its high complexity. It is also not easy to do amendment once layout change is necessary. At this point, how to find a suitable method to do analysis and prediction with the key factors of the internal bus integrity. It becomes the research topic of this paper that how to improve the success rate of the final product and shorten the overall analysis time.
This study is based on Intel Apollo Lake Platform's SATA Gen3 Port (6Gb / s), and Pass / Fail of the test signal quality is determined by eye diagram specification defined by the association . In this study, we use the professional simulation software SIWAVE and HSPICE to do the eye diagram analysis. Firstly, according to the signal integrity theory and the method of controlling signal quality known in the industrial computer board industry, we select important Bayesian factors (length, VIA number, impedance and De-Emphasis), determine the variables of the Bayesian factor, according to the Bayesian factor and variables design circuit diagram and PCB Gerber. On the one hand, get the eye height of SATA eye diagram with the simulation software. On the other hand, we can analyze the training data by Bayesian network classification method, and then bring Test Data into this prediction model to obtain the prediction result and compare it with the simulation results of the simulation software.
This study not only verifies that the Bayesian network classification can be applied to predict the high-speed differential signal SATA eye diagram of the eye is good or Bad, so that engineers can correct the design in time, but also modified the way to improve the success rate of PCB layout.
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