| Summary: | 碩士 === 國立臺灣師範大學 === 電機工程學系 === 105 === In this paper, a visual simultaneous localization and mapping probem (V-SLAM) is addressed by proposing a V-SLAM system based on linear models. Moreover, to develop a low-cost, low power comsuming, and high computational efficiency of a V-SLAM system, an FPGA-implmentation for the proposed approach is established. The proposed V-SLAM system employs SIFT feature detection and description algorithm to extract features from an image, which are subsequently used to decide whether the input image is a key-frame or not. Furthermore, map management is proposed to filter out unstable landmarks such that relative camera pose estimation can be estimated reliably. To build a consistent 3D map, landmarks are updated using an iterative linear equation which is sublinearly convergent, where the updated landmarks are introduced to estimate absolute camera pose according to a linear model. To detect any potential loop closure, another linear model is designed to describe the similarity between the previous-seen images and the current one so that looped key-frame can be found successfully. If a loop is detected, an improved trajectory bending algorithm is therefore subsequently employed to revise the states of a camera as well as landmarks. Inherited from the superiorities of parallel computation, an FPGA-implementation of the proposed V-SLAM system is developed, where One-Sided Hestenes-Jacobi algorithm is designed to provide singular value decomposition of a matrix. To verify the proposed system, exhausted simulations and experiments are introduced, where indoor small-scale as well as outdoor large-scale environments are provided. The former uses an Xtion RGB-D camera, while the latter is by means of a KITTI public dataset using stereo vision. Compared to the existing methods, the proposed approach shows unprecedent estimations according to experimental results. As for the design of hardware implementations, features from an indoor environment are provided to verify the effectiveness of the system. Experimental results show that the required computational time using FPGA is approximately 350 and 460 times faster than using a normal PC in terms of localization and mapping, respectively.
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