| Summary: | 碩士 === 國立清華大學 === 電機工程學系所 === 105 === As the semiconductor technology continues to evolve, more and more transistors can be placed on a single chip with more complex functions implemented. These complex functions are usually divided into sub-systems with possibly different clock frequencies and power supplies to achieve better performance. However it’s impossible to check timing constraints directly if signals are transmitted across different clock domains. To deal with this reliability issues, synchronizers are used to synchronize these cross-domain signals to minimize transmission errors.
Mean-time-between-failures (MTBF) is used to characterize reliability of synchronizers. Resolution time constant (τ) is an important parameter for MTBF improvement because smaller τ results in larger MTBF. We develop a simulation method which can be derived from timing window equation to measure τ accurately. Using this method we can find that it is dominated by the first stage of synchronizer. We use TSMC 65LP technology to simulate various synchronizers and find their sensitivities with repect to temperature, supply voltage, process variation, and mix V_th process with HSPICE. In additional we use two Figures of Merits (FOM) called MPDP and MPDAP to compare overall performance of different synchronizers. Last but not least, using the knowledge gained we have improved τ by more than 50% compared to the known published results.
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