Evaluation of NoC Design for Heterogeneous Multicore Systems

• Main Authors: Tsai, Shin-Ni, 蔡昕霓
• Other Authors: King, Chung-Ta
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/f2hhru

碩士 === 國立清華大學 === 資訊工程學系所 === 105 === Heterogeneous multicore systems integrate different types of processors on the same chip in order to match the workloads with the most appropriate processors. Among the different types of processors, Graphic Processing Unit (GPU) is one of the most commonly used processors, not only because of their technology maturity but also because of their high computing-power ratio. To interconnect the multiple CPUs, GPUs, caches, and memory controllers on a chip, a network-on-chip (NoC) is often used, whose design is very critical to the performance of the whole system. As CPUs and GPUs often play different roles and execute different workloads, the traffic injected into the NoC from CPUs and GPUs may have very different characteristics. GPU cores tend to generate bursty high-volume traffic, which is throughputsensitive. Therefore, the placement of GPU cores in the NoC and the network resources allocated to the GPUs should be designed carefully in order not to hinder the performance of GPUs. In this thesis, we evaluate the performance of NoC under different processor placement and network resource allocation. We use gem5-gpu simulator to simulate applications running in a heterogeneous CPU-GPU multicore system and record the memory access trace. We then modify Garnet2.0 to take the trace as input and evaluate the performance of different system configurations. It is observed that GPUs are sensitive to the proximity to memory from the evaluations. Therefore it can be referred as a critical impacting factor in terms of heterogeneous NoC design.