| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 105 === Output buffer is the interface between one chip and another. With advancement of semiconductor manufacturing technologies, the quality of data transmission affected by the environmental factors become more serious than ever.
This thesis contains two designs, namely 2 VDD output buffer with process, voltage detection and compensation, and slew rate compensation therewith.
The first topic demonstrates how to efficiently compensate slew rate provided that the signal is contanminated by environmental variations. A total of six compensation paths are used in the output stage, where 3 paths carry out compensation for process variation
and the rest aims at that of voltage variation. The accuracy of the compensation is proved to be enhanced.
The second topic is based on the result of the first topic. To reduce the impact of the leakage current which is very serious in dvanced technologies, we propose a combination approach of adding a leakage current compensation circuit, changing MOS type of output
stage, and tuning MOS length. Besides, we also seek the optimization of MOS type vs.
MOS length for the slew rate. As a consequence, the slew rate is compensated, while the leakage current is reduced.
In summary, the utilization of six compensation paths and Low Vth MOS with nonminimum size is proved to improve the slew rate compensation and reduce the leakage current. The improvement of slew rate is 39 % by simulation, and 31.4 % by on silicon
measurement.
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