A Synthesizer of Low-Leakage Logic Cells
碩士 === 國立彰化師範大學 === 電子工程學系 === 105 === The thesis presents a low leakage logic gate synthesizer implemented in C. The synthesizer can construct either a DVL+（Dual Value Logic+）gate or a complementary metal-oxide-semiconductor (CMOS) logic gate. A synthesized gate is depicted by a transistor level ci...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9ptgx4 |