A Synthesizer of Low-Leakage Logic Cells

• Main Authors: Xue,Hao-Long, 薛皓隆
• Other Authors: Wu,Tsung-Yi
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/9ptgx4

碩士 === 國立彰化師範大學 === 電子工程學系 === 105 === The thesis presents a low leakage logic gate synthesizer implemented in C. The synthesizer can construct either a DVL+（Dual Value Logic+）gate or a complementary metal-oxide-semiconductor (CMOS) logic gate. A synthesized gate is depicted by a transistor level circuit that has low leakage current consumption. The synthesizer produces all DVL+ and CMOS gates of a single-output Boolean function given by a user, and then selects the gate that has the lowest leakage consumption as the synthesis result. During the time of building the transistor level circuit of a logic gate, the synthesizer invokes Berkeley SIS to do Boolean function simplification. And then, the simplified function is translated into a SPICE file that has different input signal values and has the transistor length and width parameters. The SPICE file can be used for circuit simulation. After the construction of the SPICE file, the synthesizer invokes NanoSim to calculate the leakage current of each input condition and estimates the average leakage current of the circuit. Our experimental results show that a DVL+ gate is often better than a CMOS gate according to the leakage current consumption.