| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 105 === In this thesis, circuits were fabricated in tsmcTM 0.18-m and 90-nm CMOS process for realizing the local oscillation source in the transceiver. This thesis will introduce the drawbacks of conventional self-injection-coupled technique, and then analyzes the operation mechanism of the complementary type. Moreover, the integration of voltage-controlled oscillator and frequency divider was realized with the same architecture to realize the phase-locked loop (PLL) circuit.
The first work in Chapter 2 implements a QVCO by using self-injection-coupled technique and utilizes complementary coupled pair to resolve DC offset problem. This design was fabricated in tsmcTM 0.18-m CMOS process. The dc power consumption is 5.23 mW for a 0.75 V supply voltage. The measured tuning range is from 5.11 to 5.87 GHz. The measured phase noise is -110.95 dBc/Hz at 1 MHz offset and the phase error is 0.29. The figure of merit (FoM,FoMQ) of circuit are -178.5 dBc/Hz and -228.69 dBc/Hz, respectively. The chip area is 1.12 × 0.73 mm2.
Chapter 3 presents two circuits. One of them is a VCO integrated with a frequency divider. In VCO design, complementary cross-coupled topology is adopted. The frequency divider topology is a current mode logic divider (CML). This design was fabricated in tsmcTM 90-nm CMOS process. The dc power consumption of the VCO and CML are 2.06 mW and 4.05 mW, respectively. The measured tuning range of the VCO and CML are from 10.52 to 11.66 GHz and 5.26 to 5.82 GHz, respectively. The phase noise of the VCO and CML are -106.7 dBc/Hz and -112.3 dBc/Hz at 1 MHz offset. The figure of merit (FoM) of the VCO and CML are -184.1 dBc/Hz and -178.9 dBc/Hz, respectively. The chip area is 0.68 × 0.57 mm2.
The last work in Chapter 3 implements an X-band integer-N phase locked loop. This design was fabricated in tsmcTM 90-nm CMOS process. The division ratio of the PLL is 256. The total dc power consumption is 7.59 mW. The measured locking range is from 10.74 to 10.78 GHz with the reference frequency from 41.2 to 42.1 MHz. The measured bandwidth is 1 MHz. The reference spur and RMS jitter are -64.71 dBc and 1.41 ps, respectively. The power efficiency is 0.71. The figure of merit (FoMSpur, FoMPower, FoMJitter ) of circuit are 92.25, 0.49, -228.21, respectively. The chip area is 0.68 × 0.66 mm2.
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